Circuit models have been developed to emulate an associative network of neurons as in a human brain. One such electronic implementation of a neuron is described in "A Neuromorphic VLSI Learning System", by Alspector and Allen, Advanced Research in VLSI, Proceedings of the 1987 Stanford Conference. In general, such systems provide an electronic representation of a neuron with many weighted inputs, a summing portion and a computational portion for determining a desired functional outcome given the weighted inputs. These neurons are coupled together to form an associative network or neural network. One such prior art neural network is shown in FIG. 1 of the patent "Semiconductor Cell for Neural Network and the Like", U.S. Pat. No. 5,055,897 issued Oct. 8, 1991 and assigned to the assignee of the present invention. Another related patent application is entitled "Method of Increasing the Accuracy of an Analog Neural Network and the Like", Ser. No. 07/634,033, filed Dec. 26, 1990, and divisional application Ser. No. 07/865,451, filed Apr. 9, 1992 both assigned to the assignee of the present invention.
Training a network is necessary to make the network produce a desired output for a given input. In networks like a neural network, training the network includes programming and measuring analog levels of analog cells or floating gate devices of the network. These networks include EPROM (Electrically Programmable Read Only Memories) and EEPROM (Electrically Eraseable and Programmable Read Only Memories) devices that may use analog levels to increase storage density. In a neural network, training is accomplished by adjusting the weights for connections or synapses between neurons. Initially, all numeric weights for connections between neurons, as well as any weighting of input signals, are randomly set to various values. Signals are then inputted, and the output is observed. If an output signal is erroneous, then a mathematical computation will determine how the weights should be adjusted. Input signals are then re-applied and the output is again re-evaluated, until the output is correct. The technique for back-propagation or feedback of an error correction signal is an important characteristic in training a neural network. One such neural network well known and available in the prior art is the ETANN (Electronically Trainable Analog Neural Network).
Prior art systems exist for programming digital devices. Typically, these programming systems are used for programming EPROMs (Electrically Programmable Read Only Memories). These systems comprise a host computer to which a personal computer personal programmer (PCPP) is coupled. The PCPP is typically a circuit board that plugs into a slot in the host computer. The PCPP provides the host hardware interface to the digital device being programmed. The host computer of these prior art systems is connected to a generic universal programmer interface (GUPI) base via the PCPP. A ribbon cable is typically used to connect the PCPP to the GUPI base. A digital adaptor is then plugged into a socket on the GUPI base. The digital device being programmed is plugged into a socket on the digital adapter.
The PCPP environment with digital adapters in the prior art proved too restrictive for use in training analog devices, since it was defined with purely digital devices in mind. Since the ETANN is mostly analog, adjusting the weight of a synapse in an ETANN is not as straight forward as programming a cell in an EPROM. First, the present weight of the synapse must be read. Second, the delta from the desired weight must be calculated. Lastly, this delta value is converted to an analog programming pulse width and height. The pulse is then applied to the synapse. For these math intensive operations, the digital form of PCPP is unable to support an analog application.
Thus, a better means for training analog synapses in a neural network is needed.
Other prior art known to Applicant is "An Associative Memory Based On An Electronic Neural Network Architecture" by R. Howard et al., IEEE Transactions On Electronic Devices Vol. ED34 July 1987; "An Artificial Neural Network Integrated Circuit Based On MNOS/CCD Principles" by J. Sage, Neural Network For Computing, AIP Conference Proceedings, 1986; "A 20 V Four-Quadrant CMOS Analog Multiplier", by J. Babanezhad, IEEE Journal of Solid-Date Circuits, Vol. SC-20, December 1985; "Programmable Analog Synapses For Microelectronic Neural Networks Using a Hybrid Digital-Analog Approach", by F. J. Mack et al., IEEE International Conference on Neural Networks, Jul. 24-27, 1988, San Diego, Calif.; "VLSI for Artificial Intelligence", edited by Jose G. DelGado-Frias and Will R. Moore, Kluwer Academic Publishers, pp. 230-33, 1989; "A Pipelined Associative Memory Implemented in VLSI", by Clark et al., IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, pp. 28-34, February 1989; and "A Neuromorphic VLSI Learning System", by Alspector and Allen, Advanced Research in VLSI, Proceedings of the 1987 Stanford conference;
80170XA Data sheet January 1990, Intel Corporation Document Number ETANN-003; PA0 80170NW data sheet May 1990, Intel Corporation Document number 293xxx-001; PA0 GUPI BASE EPS/IPS C. Brabenac, B. Brooks, Dec. 17, 1985, Intel Corporation Document Number 166104; PA0 PCPP/PCPPH EPS/IPS Eng rev. 2 R. Weeden, Dec. 14, 1986, Intel Corporation Document Number 168373.